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Design of low phase noise Double frequency PLL

Description :

As technology is developing the integrated circuits need to be developed so it can works faster and more sensetive with less noise and less size. There are many designs in this domain but the problem in them is that they didn't take the size into consideration. in this work I will try to design and fabricate dual frequency Phase Locked-Loop(PLL) with less phase noise and less size. OBJECTIVE (s) 1- to reach phase noise about -114 dBc 2- to reach a size less than 2×1.5×2 mm³ SCOPE Following tasks will be undertaken as a part of the proposed research. Task 1 : design and simulate suitable inductors using CST Task 2 : design and simulate using ADS and Cadence Virtuoso: vco, frequency divider, phase frequency detector, charge pump and loop filter. Task 3: optimization using ADS and Cadnence Virtuoso Task 4: fabrication using Cadebce Virtuoso METHODOLOGY AND APPROACH to reach the stated goals, the cmos (instead of bipolar) 0.18um TSMC technology will be used. for VCO design cross-coupled structure will be used for FD design True Single Phase Clocking (TSPC) will be used for PFD design only the flip-flop topology without using separated AND Gate circuit to decrease the dead zone, will be used

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Projet présenté au CR, le : 31/10/2022

Projet achevé auprès du CR : 31/12/2025